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SV51005
2014.01.10
Document Revision History
4-41
Date
Version
Changes
May 2013
2013.05.06
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?
?
?
Added link to the known document issues in the Knowledge Base.
Updated PCLK clock sources per device quadrant.
Added PCLK networks resources and diagram for Stratix V E devices.
Updated PCLK clock sources in hierarchical clock networks in each
spine clock per quadrant diagram.
?
?
?
?
?
?
?
?
?
?
?
?
Added PCLK networks in clock network sources section.
Updated dedicated clock input pins in clock network sources section.
Added information on C output counters for PLLs.
Added power down mode in PLL features table.
Added information on PLL physical counters.
Updated the PLL locations index from CEN_X<#>_Y<#> , COR_X<#>_Y<#>
, and LR_X<#>_Y<#> to FRACTIONALPLL_X<#>_Y<#> .
Removed LVPECL I/O standard support for clock output pin pairs.
Updated PLL support for EFB mode.
Updated the scaling factors for PLL output ports.
Updated the fractional value for PLL in fractional mode.
Moved all links to the Related Information section of respective topics
for easy reference.
Reorganized content.
December 2012
June 2012
November 2011
2012.12.28
1.4
1.3
? Added note to indicate that the figures shown are the top view of the
silicon die.
? Added diagram for PLL physical counter orientation.
? Updated PLL locations diagrams.
? Removed information on pfdena PLL control signal.
? Removed information on PLL Compensation assignment in the
Quartus II software.
? Updated the fractional value for PLL in fractional mode.
? Reorganized content and updated template.
? Added Table 4 – 5 and Table 4 – 6.
? Added Figure 4 – 6, Figure 4 – 8, Figure 4 – 20, Figure 4 – 22, and Figure
4 – 33.
? Updated Table 4 – 1, Table 4 – 2, and Table 4 – 3.
? Updated Figure 4 – 3, Figure 4 – 5, Figure 4 – 17, Figure 4 – 18, Figure 4 – 19,
and Figure 4 – 21.
? Added “ PLL Migration Guidelines ” , “ Implementing Multiple PLLs in
Normal Mode and Source Synchronous Mode ” , “ Clock Switchover ” ,
and “ PLL Reconfiguration and Dynamic Phase Shift ” sections.
? Updated “ Clock Networks in Stratix V Devices ” , “ Clock Network
Sources ” , and “ Clock Multiplication and Division ” sections.
Updated Figure 4 – 19 and Figure 4 – 28.
Clock Networks and PLLs in Stratix V Devices
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